EEweb Home     ::     Graduate Courses     ::     Undergraduate Courses     ::     My Home

ABET Course Objectives and Outcomes Form

Course number and title: EE115C Digital Electronic Circuits
Credits: 4
Instructor(s)-in-charge: D. Markovic (dejan@ee.ucla.edu)
  S. Pamarti (spamarti@ee.ucla.edu)
Course type: Lecture
Required or Elective: Required for students following the CE option.
Course Schedule:
Lecture: 3 hrs/week. Meets twice weekly.
Dicussion: 1 hr/discussion section. Multiple discussion sections offered per quarter.
Outside Study: 9 hrs/week.
Office Hours: 3.5 hrs/week by instructor. 2 hrs/week by each teaching assistant.
 
Course Assessment:
Homework: 6 assignments.
Quizzes: optionally 1 quiz
Exams: 1 midterm and 1 final examination.
Design: 2 design experiments.
 
Grading Policy: Typically 15% design, 15% homework, 10% quiz, 25% midterm, 35% final.
Course Prerequisites: EE115A, CS M51A. Recommended: EE115B.
Catalog Description: Transistor-level digital circuit analysis and design. Modern logic families (static CMOS, pass-transistor, dynamic logic), integrated circuit (IC) layout, digital circuits (logic gates, flipflop/latches, counters, etc), computer-aided simulation of digital circuits.  
Textbook and any related course material:
J. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits: A Design Perspective, 2nd Edition, Prentice Hall, NJ, 2002.
 
Course Website
Additional Course Website
Topics covered in the course and level of coverage:
Introduction to digital circuits. 1.5 hrs.
Technology and layout of digital circuits. 3 hrs.
CMOS transistors for digital circuits. 3 hrs.
Static CMOS Invertors: static behavior, dynamic behavior, and power. 6 hrs.
Complex logic gates: static, dynamic behavior, and power. 6 hrs.
Advanced circuit styles. 4.5 hrs.
Sequential circuits. 4.5 hrs.
Advanced topics: clocking, data paths, interconnect. 3 hrs.
Digital design project. outside study
Course objectives and their relation to the Program Educational Objectives:  
Contribution of the course to the Professional Component:
Engineering Topics: 0 %
General Education: 0 %
Mathematics & Basic Sciences: 0 %
Expected level of proficiency from students entering the course:
Mathematics: Strong
Physics: Average
Chemistry: Not Applicable
Technical writing: Some
Computer Programming: Some
Material available to students and department at end of course:
  Available to
students
Available to
department
Available to
instructor
Available to
TA(s)
Course Objectives and Outcomes Form: X X X X
Lecture notes, homework assignments, and solutions: X X X X
Samples of homework solutions from 2 students: X
Samples of exam solutions from 2 students: X
Course performance form from student surveys: X X
Will this course involve computer assignments? NO Will this course have TA(s) when it is offered? YES

  Level of contribution of course to Program Outcomes
(a) Strong  
(c) Strong  
(e) Strong  
(i) Average  
(k) Average  
Strong: (a) (c) (e)
Average: (i) (k)

:: Upon completion of this course, students will have had an opportunity to learn about the following ::
  Specific Course Outcomes Program Outcomes
1. Understand the current equations and parasitic effects of MOS transistors. a c e
2. Apply current equations of MOS transistors. c e k
3. Understand the static operation of a CMOS inverter. c e k
4. Calculate resistances and capacitances of MOS transistors. c e k
5. Delay analysis of a CMOS inverter. c e k
6. Power analysis of a CMOS inverter. c e k
7. Physical layout of logic gates. a c e
8. Design and sizing (W/L) of simple logic gates. c e k
9. Delay analysis of a chain of logic gates. c e k
10. Calculate the delay of wires c e k
11. Operation of latches and flip-flops. a c e
12. Understand the definitions of set-up and hold times. a c e
13. Implementation of a multi-bit arithmetic element (example: adder). c e k
14. Analyze timing constraints of logic paths. c e k
15. Several homework assignments delving on core concepts and reinforcing analytical skills learned in class. a i
16. A design project, mimic of industrial environment, with design phase, implementation phase, verification phase and professional reporting phase. a c e i k
17. Opportunities to interact weekly with the instructor and the teaching assistant(s) during regular office hours and discussion sections in order to further the students' learning experience and the students' interest in the material. i

  Program outcomes and how they are covered by the specific course outcomes
(a)   Understand the current equations and parasitic effects of MOS transistors.  
  Physical layout of logic gates.  
  Operation of latches and flip-flops.  
  Understand the definitions of set-up and hold times.  
  Several homework assignments delving on core concepts and reinforcing analytical skills learned in class.  
  A design project, mimic of industrial environment, with design phase, implementation phase, verification phase and professional reporting phase.  
(c)   Understand the current equations and parasitic effects of MOS transistors.  
  Apply current equations of MOS transistors.  
  Understand the static operation of a CMOS inverter.  
  Calculate resistances and capacitances of MOS transistors.  
  Delay analysis of a CMOS inverter.  
  Power analysis of a CMOS inverter.  
  Physical layout of logic gates.  
  Design and sizing (W/L) of simple logic gates.  
  Delay analysis of a chain of logic gates.  
  Calculate the delay of wires  
  Operation of latches and flip-flops.  
  Understand the definitions of set-up and hold times.  
  Implementation of a multi-bit arithmetic element (example: adder).  
  Analyze timing constraints of logic paths.  
  A design project, mimic of industrial environment, with design phase, implementation phase, verification phase and professional reporting phase.  
(e)   Understand the current equations and parasitic effects of MOS transistors.  
  Apply current equations of MOS transistors.  
  Understand the static operation of a CMOS inverter.  
  Calculate resistances and capacitances of MOS transistors.  
  Delay analysis of a CMOS inverter.  
  Power analysis of a CMOS inverter.  
  Physical layout of logic gates.  
  Design and sizing (W/L) of simple logic gates.  
  Delay analysis of a chain of logic gates.  
  Calculate the delay of wires  
  Operation of latches and flip-flops.  
  Understand the definitions of set-up and hold times.  
  Implementation of a multi-bit arithmetic element (example: adder).  
  Analyze timing constraints of logic paths.  
  A design project, mimic of industrial environment, with design phase, implementation phase, verification phase and professional reporting phase.  
(i)   Several homework assignments delving on core concepts and reinforcing analytical skills learned in class.  
  A design project, mimic of industrial environment, with design phase, implementation phase, verification phase and professional reporting phase.  
  Opportunities to interact weekly with the instructor and the teaching assistant(s) during regular office hours and discussion sections in order to further the students' learning experience and the students' interest in the material.  
(k)   Apply current equations of MOS transistors.  
  Understand the static operation of a CMOS inverter.  
  Calculate resistances and capacitances of MOS transistors.  
  Delay analysis of a CMOS inverter.  
  Power analysis of a CMOS inverter.  
  Design and sizing (W/L) of simple logic gates.  
  Delay analysis of a chain of logic gates.  
  Calculate the delay of wires  
  Implementation of a multi-bit arithmetic element (example: adder).  
  Analyze timing constraints of logic paths.  
  A design project, mimic of industrial environment, with design phase, implementation phase, verification phase and professional reporting phase.  

:: Last modified: February 2013 by J. Lin ::

Copyright © 2003 UCLA Electrical and Computer Engineering Department. All rights reserved.
Please contact eeweb@ee.ucla.edu for comments or questions for the website.