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ABET Course Objectives and Outcomes Form

Course number and title: EE118D VLSI System Design
Credits: 4
Instructor(s)-in-charge: M. B. Srivastava (mbs@ee.ucla.edu)
Course type: Design
Required or Elective: A pathway design course.
Course Schedule:
Lecture: 4 hrs/week. Meets twice weekly.
Dicussion: 1 hr/discussion section.
Lab: 4 hrs/week. Meets one a week.
Outside Study: 8 hrs/week.
Office Hours: 2 hrs/week by instructor. 2 hrs/week by each teaching assistant.
 
Course Assessment:
Homework: 3 to 5 assignments
Labs: 3 to 4 design laboratory assignments
Exams: 1 midterm and 1 final examination.
 
Grading Policy: Typically 40% design lab, 15% homework, 20% midterm, 25% final.
Course Prerequisites: EE115C, EE M16, and EE M116D or EE M116L. Familiarity with digital circuit and logic design, and computer architecture is needed.
Catalog Description: VLSI and system-on-chip design with focus on (1) core VLSI architecture concepts such as datapath design, clocking, power, speed, area trade-off, input/output, packaging, etc. (2) behavioral, register- transfer, logic, and physical-level structured VLSI design using CAD tools and hardware description languages, (3) additional topics such as design for testability and hardware-software co-design.  
Textbook and any related course material:
¤ M. B. Srivastava, Lecture Notes on VLSI Systems Design, available online on course website.
¤ J. Rabaey, A. Chandrakasan, and B. Nicolic’, Digital Integrated Circuits, 2nd Edition, Prentice Hall, NJ, 2002.
¤ P. Ashenden, The Designers’ Guide to VHDL, 2nd Edition, Morgan Kaufman Publishing, CA, 2001.
 
Course Website
Topics covered in the course and level of coverage:
¤ Semiconductor technology trends and impact on VLSI architecture and design. 2 hrs.
¤ CMOS fabrication, design rules. 3 hrs.
¤ Methodologies for structured VLSI design. 6 hrs.
¤ VLSI system architecture, design, and optimizations for performance and power. 8 hrs.
¤ Design for test. 5 hrs.
¤ Parasitics and interconnects. 8 hrs.
¤ Hardware description languages: concepts and tools. 6 hrs.
¤ Software-programmable processor cores. 2 hrs.
¤ Application of CAD tools to design VLSI systems based on above concepts. Outside study and design lab
Course objectives and their relation to the Program Educational Objectives: This is an elective course primarily targeted at computer engineering majors. The goal of the course is to introduce architecture and design concepts underlying modern complex VLSIs and system-on-chips. The lectures build upon students’ prior knowledge of digital circuits, digital logic, and computer architecture concepts to teach how complex chip-scale systems can be designed. The concurrent labs make the students apply the concepts learnt in the lectures towards design of actual VLSI subsystems from high level specifications, and culminates in a course project involving the hardware-software design of a modest complexity chip all the way from specification, modeling, synthesis, and physical design. The team project is run as a competition targeting a design metric and involves a final public presentation of the results by the students to their peers in the class.  
Contribution of the course to the Professional Component:
Engineering Topics: 100 %
General Education: 0 %
Mathematics & Basic Sciences: 0 %
Expected level of proficiency from students entering the course:
Mathematics: Average
Physics: Average
Chemistry: Not Applicable
Technical writing: Strong
Computer Programming: Strong
Material available to students and department at end of course:
  Available to
students
Available to
department
Available to
instructor
Available to
TA(s)
Course Objectives and Outcomes Form: X X
Lecture notes, homework assignments, and solutions: X
Samples of homework solutions from 2 students: X
Samples of lab reports from 2 students: X
Samples of exam solutions from 2 students: X
Course performance form from student surveys: X X
End-of-course Instructor Survey: X
Will this course involve computer assignments? NO Will this course have TA(s) when it is offered? YES

  Level of contribution of course to Program Outcomes
(a) Strong  
(b) Average  
(c) Strong  
(d) Average  
(e) Strong  
(g) Some  
(i) Average  
(k) Average  
Strong: (a) (c) (e)
Average: (b) (d) (i) (k)
Some: (g)

:: Upon completion of this course, students will have had an opportunity to learn about the following ::
  Specific Course Outcomes Program Outcomes
1. Modeling and simulation of digital VLSI systems using hardware design language. a b c d e k
2. Synthesis of digital VLSI systems from register-transfer or higher level descriptions in hardware design languages. a b c d e k
3. Concept of design rules. e
4. Trends in semiconductor technology, and how it impacts scaling and performance. a c
5. VLSI design methodologies - the various steps and tools, the implementation choices, and good architecture practices. a c
6. Datapath design and optimization via transformations such as pipelining, parallelism, retiming, unfolding. a c
7. Low-power design concepts and voltage-frequency scaling. a c
8. Design for test - basic concepts, fault models (stuck-at) for combinational circuits, fault equivalence and dominance, test-vector generation, scan-path based testing. a c
9. Parasitics and interconnects: modeling and estimation of R, C, and L parasitics, effect of technology scaling, sheet resistance, techniques to cope with ohmic drop and capacitive cross talk, sizing cascaded buffers, estimating RC delay, inductive effects. a c
10. Understanding a hardware design language such as VHDL in detail - syntax as well as how it works under the hood for simulation and synthesis. a c k
11. Several homework assignments delving on core concepts and reinforcing analytical skills learned in class. a i
12. Several lab team assignments to design actual VLSI subsystems from high level specifications, culminating in a course project involving the hardware-software design of a modest complexity chip all the way from specification, modeling, and synthesis. a b c d e g k
13. Opportunities to interact weekly with the instructor and the teaching assistant(s) during regular office hours and discussion sections in order to further the students' learning experience and the students' interest in the material. i

  Program outcomes and how they are covered by the specific course outcomes
(a) ¤  Modeling and simulation of digital VLSI systems using hardware design language.  
¤  Synthesis of digital VLSI systems from register-transfer or higher level descriptions in hardware design languages.  
¤  Trends in semiconductor technology, and how it impacts scaling and performance.  
¤  VLSI design methodologies - the various steps and tools, the implementation choices, and good architecture practices.  
¤  Datapath design and optimization via transformations such as pipelining, parallelism, retiming, unfolding.  
¤  Low-power design concepts and voltage-frequency scaling.  
¤  Design for test - basic concepts, fault models (stuck-at) for combinational circuits, fault equivalence and dominance, test-vector generation, scan-path based testing.  
¤  Parasitics and interconnects: modeling and estimation of R, C, and L parasitics, effect of technology scaling, sheet resistance, techniques to cope with ohmic drop and capacitive cross talk, sizing cascaded buffers, estimating RC delay, inductive effects.  
¤  Understanding a hardware design language such as VHDL in detail - syntax as well as how it works under the hood for simulation and synthesis.  
¤  Several homework assignments delving on core concepts and reinforcing analytical skills learned in class.  
¤  Several lab team assignments to design actual VLSI subsystems from high level specifications, culminating in a course project involving the hardware-software design of a modest complexity chip all the way from specification, modeling, and synthesis.  
(b) ¤  Modeling and simulation of digital VLSI systems using hardware design language.  
¤  Synthesis of digital VLSI systems from register-transfer or higher level descriptions in hardware design languages.  
¤  Several lab team assignments to design actual VLSI subsystems from high level specifications, culminating in a course project involving the hardware-software design of a modest complexity chip all the way from specification, modeling, and synthesis.  
(c) ¤  Modeling and simulation of digital VLSI systems using hardware design language.  
¤  Synthesis of digital VLSI systems from register-transfer or higher level descriptions in hardware design languages.  
¤  Trends in semiconductor technology, and how it impacts scaling and performance.  
¤  VLSI design methodologies - the various steps and tools, the implementation choices, and good architecture practices.  
¤  Datapath design and optimization via transformations such as pipelining, parallelism, retiming, unfolding.  
¤  Low-power design concepts and voltage-frequency scaling.  
¤  Design for test - basic concepts, fault models (stuck-at) for combinational circuits, fault equivalence and dominance, test-vector generation, scan-path based testing.  
¤  Parasitics and interconnects: modeling and estimation of R, C, and L parasitics, effect of technology scaling, sheet resistance, techniques to cope with ohmic drop and capacitive cross talk, sizing cascaded buffers, estimating RC delay, inductive effects.  
¤  Understanding a hardware design language such as VHDL in detail - syntax as well as how it works under the hood for simulation and synthesis.  
¤  Several lab team assignments to design actual VLSI subsystems from high level specifications, culminating in a course project involving the hardware-software design of a modest complexity chip all the way from specification, modeling, and synthesis.  
(d) ¤  Modeling and simulation of digital VLSI systems using hardware design language.  
¤  Synthesis of digital VLSI systems from register-transfer or higher level descriptions in hardware design languages.  
¤  Several lab team assignments to design actual VLSI subsystems from high level specifications, culminating in a course project involving the hardware-software design of a modest complexity chip all the way from specification, modeling, and synthesis.  
(e) ¤  Modeling and simulation of digital VLSI systems using hardware design language.  
¤  Synthesis of digital VLSI systems from register-transfer or higher level descriptions in hardware design languages.  
¤  Concept of design rules.  
¤  Several lab team assignments to design actual VLSI subsystems from high level specifications, culminating in a course project involving the hardware-software design of a modest complexity chip all the way from specification, modeling, and synthesis.  
(g) ¤  Several lab team assignments to design actual VLSI subsystems from high level specifications, culminating in a course project involving the hardware-software design of a modest complexity chip all the way from specification, modeling, and synthesis.  
(i) ¤  Several homework assignments delving on core concepts and reinforcing analytical skills learned in class.  
¤  Opportunities to interact weekly with the instructor and the teaching assistant(s) during regular office hours and discussion sections in order to further the students' learning experience and the students' interest in the material.  
(k) ¤  Modeling and simulation of digital VLSI systems using hardware design language.  
¤  Synthesis of digital VLSI systems from register-transfer or higher level descriptions in hardware design languages.  
¤  Understanding a hardware design language such as VHDL in detail - syntax as well as how it works under the hood for simulation and synthesis.  
¤  Several lab team assignments to design actual VLSI subsystems from high level specifications, culminating in a course project involving the hardware-software design of a modest complexity chip all the way from specification, modeling, and synthesis.  

:: Last modified: September 2007 by M. B. Srivastava ::

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