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Course number and title: EE215E Signaling and Synchronization
Credits: 4
Instructor(s)-in-charge: S. Pamarti (spamarti@ee.ucla.edu)
Course type: Lecture
Required or Elective: A Circuits and Embedded Systems course.
Course Schedule:
Lecture: 4 hrs/week.
Outside Study: 8 hrs/week.
Office Hours: 2 hrs/week.
 
Course Assessment:
Project Reports: 1 project.
Exams: 1 midterm and 1 final examination.
 
Grading Policy: Typically, 20% midterm, 30% final, 50% project.
Course Prerequisites: EE215A, EEM216A
Catalog Description: Analysis and design of circuits for synchronization and communication for VLSI systems. Use of both digital and analog design techniques to improve data rate of electronics between functional blocks, chips, and systems. Advanced clocking methodologies, phase-locked loop design for clock generation, and high-performance wire-line transmitters, receivers, and timing recovery circuits.  
Textbook and any related course material:
Lecture notes by instructor.
 
Course Website
Topics covered in the course:
Oscillator design.
Clock generator first-order (DLL) loop analysis.
Clock generator higher-order (PLL) loop analysis.
Clock generator (PLL) loop design.
Data recovery phase detection.
Transmitter design.
Receiver design.
I/O channel equalization techniques.
Will this course involve computer assignments? NO Will this course have TA(s) when it is offered? NO

:: Last modified: February 2013 by J. Lin ::

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