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ABET Course Objectives and Outcomes Form

Course number and title: EEM116D Digital Design Project Laboratory
Credits: 4
Instructor(s)-in-charge: L. He (lhe@ee.ucla.edu)
Course type: Design
Required or Elective: A pathway course.
Course Schedule:
Lecture: 3 hrs/week. Meets twice weekly.
Dicussion: 3 hrs/discussion section.
Outside Study: 6 hrs/week.
Office Hours: 2 hrs/week by instructor. 2 hrs/week by each teaching assistant.
 
Course Assessment:
Design: 4 projects.
 
Grading Policy: Typically 80% design, 20% participation.
Course Prerequisites: EEM116C
Catalog Description: Design and implementation of complex digital systems using field programmable gate arrays. Students work in teams to develop and implement designs and document and given oral presentations on their work.  
Textbook and any related course material:
K. C. Chang, Digital Systems Design with VHDL and Synthesis: An Integrated Approach, Wiley-IEEE Press, NY, 1999.
 
Course Website
Topics covered in the course and level of coverage:
Introduction to VHDL syntax. 2 hrs.
VHDL for simulation. 3 hrs.
VHDL for synthesis. 2 hrs.
Project management overview. 3 hrs.
AMD 2901 bit-sliced micro-engine. 2 hrs.
AMD 2910 bit-sliced microcontroller. 2 hrs.
Testing strategies in depth. 3 hrs.
System requirements for full processor design. 3 hrs.
Course objectives and their relation to the Program Educational Objectives: This is a required course for electrical engineering, computer engineering, and biomedical engineering majors. The goal of the course is to introduce students to the fundamentals of digital system design, to expose them to design tools and practices, and to ask them to complete a large coherent design.  
Contribution of the course to the Professional Component:
Engineering Topics: 100 %
General Education: 0 %
Mathematics & Basic Sciences: 0 %
Expected level of proficiency from students entering the course:
Mathematics: Not Applicable
Physics: Not Applicable
Chemistry: Not Applicable
Technical writing: Some
Computer Programming: Average
Material available to students and department at end of course:
  Available to
students
Available to
department
Available to
instructor
Available to
TA(s)
Course Objectives and Outcomes Form: X X X X
Lecture notes, homework assignments, and solutions: X X X X
Samples of lab reports from 2 students: X
Course performance form from student surveys: X X
End-of-course Instructor Survey: X X
Will this course involve computer assignments? NO Will this course have TA(s) when it is offered? YES

  Level of contribution of course to Program Outcomes
(a) Strong  
(b) Strong  
(c) Strong  
(d) Average  
(e) Strong  
(g) Average  
(i) Strong  
(m) Some  
Strong: (a) (b) (c) (e) (i)
Average: (d) (g)
Some: (m)

:: Upon completion of this course, students will have had an opportunity to learn about the following ::
  Specific Course Outcomes Program Outcomes
1. Design and implement combinational logic in VHDL for simulation. a b e
2. Design and implement sequential logic in VHDL for simulation. a b e
3. Use VHDL for synthesis of combinational logic. a
4. Use VHDL for synthesis of sequential logic. a m
5. Use CAD tools for visualization of logic simulation. a m
6. Implement logic designs using FPGAs. a b
7. Optimize a logic design to achieve a higher clock rate after mapping to an FPGA. a b c
8. Optimize a logic design to require fewer physical resources after mapping to an FPGA. a b c
9. Design of microprogrammable devices using bit-sliced components. a b c e g
10. Use microprograming to implement a design on bit-sliced components. a b c g
11. An opportunity to practice teamwork with students from EE and CS and to document and make a final oral presentation on design project. b c d g
12. Four significant design projects, each building upon the predecessors and using the tools discussed in lecture. a i
13. One significant oral presentation before the entire class. b c g
14. Opportunities to interact weekly with the instructor and the teaching assistant(s) during regular office hours and discussion sections in order to further the students' learning experience and the students' interest in the material. i

  Program outcomes and how they are covered by the specific course outcomes
(a)   Design and implement combinational logic in VHDL for simulation.  
  Design and implement sequential logic in VHDL for simulation.  
  Use VHDL for synthesis of combinational logic.  
  Use VHDL for synthesis of sequential logic.  
  Use CAD tools for visualization of logic simulation.  
  Implement logic designs using FPGAs.  
  Optimize a logic design to achieve a higher clock rate after mapping to an FPGA.  
  Optimize a logic design to require fewer physical resources after mapping to an FPGA.  
  Design of microprogrammable devices using bit-sliced components.  
  Use microprograming to implement a design on bit-sliced components.  
  Four significant design projects, each building upon the predecessors and using the tools discussed in lecture.  
(b)   Design and implement combinational logic in VHDL for simulation.  
  Design and implement sequential logic in VHDL for simulation.  
  Implement logic designs using FPGAs.  
  Optimize a logic design to achieve a higher clock rate after mapping to an FPGA.  
  Optimize a logic design to require fewer physical resources after mapping to an FPGA.  
  Design of microprogrammable devices using bit-sliced components.  
  Use microprograming to implement a design on bit-sliced components.  
  An opportunity to practice teamwork with students from EE and CS and to document and make a final oral presentation on design project.  
  One significant oral presentation before the entire class.  
(c)   Optimize a logic design to achieve a higher clock rate after mapping to an FPGA.  
  Optimize a logic design to require fewer physical resources after mapping to an FPGA.  
  Design of microprogrammable devices using bit-sliced components.  
  Use microprograming to implement a design on bit-sliced components.  
  An opportunity to practice teamwork with students from EE and CS and to document and make a final oral presentation on design project.  
  One significant oral presentation before the entire class.  
(d)   An opportunity to practice teamwork with students from EE and CS and to document and make a final oral presentation on design project.  
(e)   Design and implement combinational logic in VHDL for simulation.  
  Design and implement sequential logic in VHDL for simulation.  
  Design of microprogrammable devices using bit-sliced components.  
(g)   Design of microprogrammable devices using bit-sliced components.  
  Use microprograming to implement a design on bit-sliced components.  
  An opportunity to practice teamwork with students from EE and CS and to document and make a final oral presentation on design project.  
  One significant oral presentation before the entire class.  
(i)   Four significant design projects, each building upon the predecessors and using the tools discussed in lecture.  
  Opportunities to interact weekly with the instructor and the teaching assistant(s) during regular office hours and discussion sections in order to further the students' learning experience and the students' interest in the material.  
(m)   Use VHDL for synthesis of sequential logic.  
  Use CAD tools for visualization of logic simulation.  

:: Last modified: September 2007 by L. He ::

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