
Program outcomes and how they are covered by the specific course outcomes 



(a) 
¤ 
Design and implement combinational logic in VHDL for simulation. 



¤ 
Design and implement sequential logic in VHDL for simulation. 



¤ 
Use VHDL for synthesis of combinational logic. 



¤ 
Use VHDL for synthesis of sequential logic. 



¤ 
Use CAD tools for visualization of logic simulation. 



¤ 
Implement logic designs using FPGAs. 



¤ 
Optimize a logic design to achieve a higher clock rate after mapping to an FPGA. 



¤ 
Optimize a logic design to require fewer physical resources after mapping to an FPGA. 



¤ 
Design of microprogrammable devices using bitsliced components. 



¤ 
Use microprograming to implement a design on bitsliced components. 



¤ 
Four significant design projects, each building upon the predecessors and using the tools discussed in lecture. 

  

(b) 
¤ 
Design and implement combinational logic in VHDL for simulation. 



¤ 
Design and implement sequential logic in VHDL for simulation. 



¤ 
Implement logic designs using FPGAs. 



¤ 
Optimize a logic design to achieve a higher clock rate after mapping to an FPGA. 



¤ 
Optimize a logic design to require fewer physical resources after mapping to an FPGA. 



¤ 
Design of microprogrammable devices using bitsliced components. 



¤ 
Use microprograming to implement a design on bitsliced components. 



¤ 
An opportunity to practice teamwork with students from EE and CS and to document and make a final oral presentation on design project. 



¤ 
One significant oral presentation before the entire class. 

  

(c) 
¤ 
Optimize a logic design to achieve a higher clock rate after mapping to an FPGA. 



¤ 
Optimize a logic design to require fewer physical resources after mapping to an FPGA. 



¤ 
Design of microprogrammable devices using bitsliced components. 



¤ 
Use microprograming to implement a design on bitsliced components. 



¤ 
An opportunity to practice teamwork with students from EE and CS and to document and make a final oral presentation on design project. 



¤ 
One significant oral presentation before the entire class. 

  

(d) 
¤ 
An opportunity to practice teamwork with students from EE and CS and to document and make a final oral presentation on design project. 

  

(e) 
¤ 
Design and implement combinational logic in VHDL for simulation. 



¤ 
Design and implement sequential logic in VHDL for simulation. 



¤ 
Design of microprogrammable devices using bitsliced components. 

  

(g) 
¤ 
Design of microprogrammable devices using bitsliced components. 



¤ 
Use microprograming to implement a design on bitsliced components. 



¤ 
An opportunity to practice teamwork with students from EE and CS and to document and make a final oral presentation on design project. 



¤ 
One significant oral presentation before the entire class. 

  

(i) 
¤ 
Four significant design projects, each building upon the predecessors and using the tools discussed in lecture. 



¤ 
Opportunities to interact weekly with the instructor and the teaching assistant(s) during regular office hours and discussion sections in order to further the students' learning experience and the students' interest in the material. 

  

(m) 
¤ 
Use VHDL for synthesis of sequential logic. 



¤ 
Use CAD tools for visualization of logic simulation. 

  